1. Field of the Invention
The present invention relates to a display and its driving method, and more particularly to a display and its driving method for inputting image signals of various standards into the panel having only a predefined number of rows.
2. Background Art
Recently, thin type flat displays as a computer to human interface, in place of CRT (Cathode Ray Tube), have become an important device to extend the multi-media market. As the flat display, an LCD (Liquid Crystal Display), a PDP (Plasma Display) and an electron beam flat display have become widely accepted. Particularly, the liquid crystal display has gained a large market along with the spread of small-sized personal computers. Among the types of liquid crystal displays, the active matrix liquid crystal display achieves greater contrast over the whole screen because of the absence of crosstalk, as compared with a simple matrix liquid crystal display such as STN. Therefore, the active matrix liquid crystal display has drawn the public's attention not only as the display for small personal computers, but also as the view finder for video cameras, projectors, and thin type televisions.
The active matrix liquid crystal display is classified into TFT and diode types. FIG. 33A is a block diagram of the image signal input for TFT image display. 20 is a display pixel unit having pixels arranged in a matrix, 40 is a vertical scan circuit for selecting the display row, 30 is a sampling circuit for color image signal, and 80 is a horizontal scan circuit for outputting the sampling signal.
A unit pixel of the display pixel unit 20 is composed of a switching element 11, a liquid crystal material 15, and a pixel capacitor 12. When the switching element 11 is a TFT (thin film transistor), a gate line 13 connects the gate electrode of the TFT to the vertical scan circuit 40, one terminal of pixel capacitor 12 for each of all the pixels being connected commonly to a common electrode 21 of an opposed substrate, to which a common electrode voltage V.sub.LC is applied. When the switching element 11 is a diode (including Metal/Insulator/Metal element), the scan electrode runs transversely across the opposed substrate to connect to the vertical scan circuit 20. An input terminal of the switching element 11 is connected by a vertical data line to the sampling circuit 30. Whether TFT or diode, a vertical data line 14 connects the input terminal of the switching element 14 to the sampling circuit 30, and an output terminal of the switching element 14 is connected to the other terminal of the pixel capacitor 12.
A control circuit 140 separates an image signal into necessary signals for the vertical scan circuit 40, the horizontal scan circuit 80 or a signal processing circuit 120. The signal processing circuit 120 performs a gamma processing in view of the liquid crystal characteristics, or an inversion signal processing for longer life of the liquid crystal to output a color image signal (red, blue, green) to the sampling circuit 30.
FIG. 33B is a detail equivalent circuit diagram of the display pixel unit 20 and the sampling circuit 30 for TFT color. 10 is a unit pixel for each color. The pixels (R, G, B) are arranged in delta configuration, the same color being allocated on either side of the data line 14 (d1, d2, . . . ) for every row, and connected to the data line 14 (d1, d2, . . . ). The sampling circuit 30 is comprised of switching transistors (sw1, sw2, . . . ) and capacitors (parasitic capacitor and pixel capacitor of the data line 14). An image signal input line 16 is comprised of a signal line dedicated for each color of RGB. The switching transistors (sw1, sw2, . . . ) sample each color signal from the image signal input line 16 in accordance with a pulse (.phi.h1, .phi.h2, . . . ) from the horizontal scan circuit 80, and transfer each color signal to each pixel through the data line 14 (d1, d2, . . . ). And they send pulses (.phi.g1, .phi.g2, . . . ) from the vertical scan circuit 40 to the TFT gate of pixels, and write a signal into each pixel by selecting the row. In this way, the pulse (.phi.g1, .phi.g2, . . . ) turns on the TFT 11 contained in each row, so that the image signal for one horizontal scan in each corresponding row is written into all pixels contained in each row. It is noted that the image signal for one horizontal scan is thereafter referred to as 1H signal.
The liquid crystal display displays a television signal or a personal computer signal. However, there are a variety of standards for these signals, whereby it is necessary to normally fabricate the panel for liquid crystal display of the type that conforms to the respective standard utilized. On the other hand, there exists a liquid crystal display for displaying the signal of various standards on one panel through appropriate signal processing. For example, a liquid crystal display is provided which displays the image of PAL (Phase Alternation by Line) system having more scan lines than the NTSC (National Television System Committee) system on the panel only having the rows corresponding to the number of scan lines in the NTSC system. Such display examples were disclosed in Japanese Laid-Open Patent Application No. 2-182087 or Japanese Laid-Open Patent Application No. 5-37909. In these publications, processing for thinning out some 1H signals from the image signal according to the PAL system is adopted. Specifically, in order to transform the effective number of scan lines (280) for one field in the
system into the 240 lines of the NTSC system, the image signal is thinned out at a rate of 1 line for every 7 lines. FIG. 9 represents a specific example of this thinning out method. The image signal of the PAL system is written on a liquid crystal display only having the rows for one field (i.e., half rows of one frame) of the NTSC system. If the image signal of NTSC system is input, 1H signal o1, o2, . . . for odd field, or 1H signal e1, e2, . . . for even field is written sequentially into each row (L1, L2, . . . ) for the liquid crystal display. If the image signal of PAL system is input, the thinning out processing is performed, because there are more scan lines than the NTSC system. As an enable circuit erases a write instruction into the row (L9) upon a horizontal gate pulse which the vertical scan circuit outputs, 1H signal o7 (e9) is thinned out. And as 1H signal o7 (e10) is written for the next 1H period, 1H signal o7 (e9) is not displayed. .DELTA. indicates a 1H signal which is thinned out. Beside, there are two-row simultaneous driving in which 1H signal is written into adjacent two rows on a panel having the rows of two field (i.e., one frame), and accordingly two-row interpolation driving. In this case, like the signal input onto the panel only having the rows for one field, the image signal of the standard of having more scan lines than one frame of the panel is displayed by completely thinning out particular 1H signals.
In the display as described above, there is a drawback that because 1H signal is completely thinned out, the image is distorted so that the character or fine line of image in the vertical direction on the screen is not displayed, particularly that the contour is less visible. To overcome this drawback of image distortion, there is disclosed a system in Japanese Laid-Open Patent Application No. 5-236453. This system once writes the image signal of interlace system into the memory for the conversion into the image signal of non-interlace system. And image distortion is moderated by thinning out only one row, instead of thinning out two rows conventionally. Also, the similar method was disclosed in Japanese Laid-Open Patent Application No. 5-100641.
On the other hand, when the image signal is input into the liquid crystal display, it is common that the image signal is made the alternating current to prevent the burning of liquid crystal material. Also, if the spatial distribution and the temporal distribution of the panel is observed microscopically, the central voltage is preferably 0. Namely, it is preferable that adjacent rows are reversely polarized, and the polarity in the same row is reversed in a short time. This is true with a plasma display and an electron beam flat display in which if deflected signal voltage is input for long time, the electrode is corroded and the element is deteriorated. In this respect, because Japanese Laid-Open Patent Application No. 5-236435 as above cited does not consider the image signal that is made the alternating current, the image signal of the same polarity succeeds in the row direction by making the scanning for thinning out, resulting in a possibility that if taking notice of three rows, the central voltage of the image signal will greatly deviate from 0. Also, the above-mentioned No. 5-100641 discloses a method of inputting the image signal having a different polarity for each row, but this method requires a large amount of memory, resulting in a complicated circuit. Thus, the present invention has a subject to provide a display capable of displaying the image signal of various standards while reducing image distortion associated with the scan for thinning out as much as possible, thereby inputting reversely the image signal optimally, only with the addition of a simple circuit.